1. Field of the Invention
The present disclosure relates generally to the field of semiconductor packaging. More particularly, the present disclosure relates to a wafer level package (WLP) with a Through Silicon Via-less (TSV-less) interposer.
2. Description of the Prior Art
A 2.5D semiconductor package such as CoWoS (Chip-on-Wafer-on-Substrate) is known in the art. CoWoS (Chip-on-Wafer-on-Substrate) typically uses Through Silicon Via (TSV) technology to integrate multiple chips into a single device. This architecture provides higher density interconnects, decreases global interconnect length, and lightens associated RC loading, resulting in enhanced performance and reduced power consumption on a smaller form factor.
As known in the art, the 2.5D semiconductor package places several die side-by-side on a TSV silicon interposer. The TSV silicon interposer is costly because fabricating the interposer substrate with TSVs is a complex process. Thus, forming WLP products that includes an interposer having TSVs may be undesirable for certain applications.
Typically, the reliability test or yield test is performed after all the semiconductor dies are mounted on the interposer and encapsulated by a molding compound. However, such approach has a higher risk of known good die loss. Further, the thick layer of the molding compound results in increased warping of the packaging due to coefficient of thermal expansion (CTE) mismatch, and the thickness of the packaging. It is known that wafer warpage continues to be a concern.
Warpage can prevent successful assembly of a die-to-wafer stack because of the inability to maintain the coupling of the die and wafer. Warpage issue is serious, especially in a large sized wafer, and has raised an obstacle to a wafer level semiconductor packaging process that requires a fine-pitch RDL process. Therefore, there remains a need in the art for an improved method of manufacturing wafer level packages.